1. Field of the Invention
Embodiments of the present invention generally relate to a method of forming a silicon layer. More particularly, embodiments of the invention relate to methods of forming hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers for electrodes in semiconductor devices.
2. Description of the Related Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. As semiconductor device sizes decrease, new methods of depositing or forming the materials of the components of semiconductor devices are required to provide components having the appropriate characteristics to maintain or enhance the performance of the devices compared to prior, larger devices.
Many methods of depositing silicon or silicon-containing layers have been developed as silicon is used extensively in semiconductor device fabrication. For example, methods of depositing silicon layers having different grain sizes have been developed to form silicon layers suitable for different uses. In one example, methods of forming hemispherical grained silicon (HSG) for a bottom electrode of a DRAM device have been developed. Hemispherical grained silicon has a textured surface that provides a significantly larger surface area than a smooth surface and thus provides an increased capacitance for a DRAM capacitor containing a hemispherical grained silicon electrode.
Prior methods of forming hemispherical grained silicon have typically included depositing an amorphous silicon layer and then performing a time consuming annealing step to convert the amorphous silicon layer into a hemispherical grained silicon layer. The prior methods have also required a narrow range of process conditions that can be difficult to achieve.
Methods of forming silicon layers for electrodes in other devices have also been developed. For example, a method of forming a silicon bi-layer for gate electrodes has been developed. This method includes depositing a lower polysilicon layer having a random grain structure followed by an upper polysilicon layer having a columnar grain structure. The columnar grain structure provides relatively few grain boundaries in the silicon bi-layer. It has been observed that a large number, i.e., thousands, of grain boundaries provide enhanced electrical properties, such as increased carrier mobility in a gate structure. However, it has proven challenging to develop methods of forming a polysilicon layer that has many grain boundaries, uniform grain structure and size, a low film roughness such that subsequently deposited layers adhere well to the polysilicon layer, and that maintains its grain size and structure after subsequent semiconductor processing steps.
Thus, there remains a need for methods of forming silicon layers that may be used as electrodes in semiconductor devices.